El foro INTEL MICROCONTROLADOR INTEL 8051
	Ver todas las instrucciones
	Enviar tus instrucciones
	Inscribirse Identificarse
INSTRUCCIONES POR CATEGORIA Electrodomésticos Vídeo & Sonido Auto & Otros vehículos Telefonía Informática Foto & Vídeo Música Material deportivo Casa, bricolaje & Jardín Juegos de vídeo & Programas Joya & Reloj Bebe & Juguete Higiene & Salud Otros

MCS@51 MICROCONTROLLER FAMILY USER'S MANUAL ORDER NO.: 272383-002 FEBRUARY 1994 Intel Corporation makes no warrsnfy for the uee of ite products and assumes no responsibility for any ewors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notk Contact your local Intel sales office or your distributor to obtain the latest speoificationa before placing your product order. MDS is an ordering code only and is not usad ae a product name or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH trademark or products, are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH q Ofher brands and names are the properly of their respective owners, Additional copies of this document or other Intel literature maybe obtained from: Intel Corporation Literature Selas P.O. Box 7S41 Mt. Prospect, IL 6005S-7641 or call 1-800-879-4683 c-INTELCORPORATION, 1093 PAGE MCS" 51 CONTENTS MICROCONTROLLER c"*pTf== 1 FAMILY MCS 51 Family of Microcontrollers Archkedural Ovewiew .............................l-l USER'S MANUAL CHAPTER 2 MCS 51 Programmer's Guide and Instruction Set ..........................................2-l CHAPTER 3 8051, 8052 and 80C51 Hardware Description ...............................................3.l CHAPTER 4 8XC52J54/58 Hardware Description ............4-1 CHAPTER 5 8XC51 FX Hardware Description .................5-1 CHAPTER 6 87C51GB Hardware Description .................8-1 CHAPTER 7 83CI 52 Hardware Description ....................7-1 MCS@ 51 Family of Microcontrollers Architectural Overview 1 MCS@51 FAMILY OF MICROCONTROLLERS ARCHITECTURAL OVERVIEW CONTENTS INTRODUCTION PAGE .........................................1-3 CHMOS Devices .....".....'......." .....-.............I-5 M;~$&:RGA-~oN INMc- 51 Lo ical Separation of Program and Data h emoy ....................................................l+ Program Memo~ .........................................l-7 .................................................1-6 Data Memory ...............................................1 -8 THE MC951 INSTRUCTION SET .............1 -9 Program Status Word ..................................1 -9 Addressing Modes .....................................l-l O Arithmetic Instructions ...............................1-10 Logical lnstrudions Data Tran#ers ....................................l.l2 ...........................................l.l2 Boolean Instructions ..................................1-14 Jump Instructions ......................................1-16 CPU TIMING .............................................l-l7 Machine Cycles .........................................1-18 Interrupt Structure ......................................l.2O ADDITIONAL REFERENCES ...................1 -22 1-1 ir&L INTRODUCTION The8051 M~@.51 ARCHITECTURAL OVERVIEW is the original member of the MCW-51 family, and is the core for allMCS-51 devices. The features of the 8051 core are q 8-bit CPU optimized for control applications q Extensive Boolean processing (Single-blt logic) capabtilties q q q q q q q q q 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytesof on-chip Data RAM 32 bidirectional and individually addressable 1/0 lines Two 16-bit timer/counters Full duplex UART 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator The basic architectural structure of this 8051 core is shown in Figure L EXTERNAL INTERRUPTS ,, I I COUNTER INPUTS w II BUS CONTROL H 4 1/0 PORTS H 11 Po P2 PI P3 AODRESS/DATA Q SERIAL PORT TXO RXD 270251-1 Figure 1. Block Diagram of the 8051 Core 1-3 intd. MCS@-51 ARCHITECTURAL OVERVIEW 1-4 i~. MCS@'-5l ARCHITECTURAL OVERVIEW 1-5 i~. M~@.51 ARCHITECTURAL OVERVIEW * ----------- 8 1 1 1 1 1 1 1 I 1 PROORAMMrhtosv (REM ONLY) -------------FFFFw T - I o 8 0 0 8 0 I I I , 0 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 I , B I I $ s -----------------------t 8 I 1 I 8 I I I : o # 8 9 8 8 0 0 9 t # I , 1 : FfH: OATAMEMORY (RW/WRlT2) EXIERNALm EXTERNAL - 0 9 1 I : # G=o o 2STERNAL 0 1 0 @ * I : q - ---------- ..... 8 8 I I 0 I * 0 I I # I I I I I I 1 : 1 I I IN7ERNM ------ m.1 IN7ERNAL : : 0 9 * I I I 0000 --------.! 0: 9, e, 9 0 9 8 1 I ,1+ 00 1 q-------- 0000 --------..- J: -. -.-: tiR 1 I 1 1 0 1 1 I 1% Figure 2. MCW'-51 Memory Structure 270251-2 CHMOS Devices Functionally, the CHMOS devices (designated with "C" in the middle of the device name) me all fiuy compatible with the 8051, but being CMOS, draw less current than an HMOS counterpart. To further exploit the power savings available in CMOS circuitry, two reduced power modes are added q MEMORY ORGANIZATION MCS@-51 DEVICES Logical Separation Data Memory IN of Program and Software-invoked Idle Mode, during which the CPU is turned off while the RAM and other on-chip peripherals continue operating. In this mode, current draw is reduced to about 15% of the current drawn when the device is fully active. Software-invoked Power Down Mode, during which all on-chip activities are suspended. The on-chip RAM continues to hold its data. In this mode the device typically draws less than 10 pA. q AU MCS-51 devices have separate address spacea for Program and Data Memory, as shown in Figure 2. The logical separation of Program and Data Memory allows the Data Memory to be acceased by 8-bit addressea, which can be more quickly stored and manipulated by an 8-bit CPU. Nevertheless, ld-bh Data Memory addresses can also be generated through the DPTR register. Program Memory can only be read, not written to. There can be up to 64K bytes of Program Memory. In the ROM and EPROM versions of these devices the loweat 4K, 8K or 16K bytes of Program Memory are provided on-chip. Refer to Table 1 for the amount of on-chip ROM (or EPROM) on each device. In the ROMleas versions all Program Memory is external. The read strobe for external Program Memory is the signal PSEN @rogram Store Enable). Although the 80C51BH is functionally compatible with its HMOS counterpart, s~lc differeneea between the two types of devices must be considered in the design of an application circuit if one wiahea to ensure complete interchangeability between the HMOS and CHMOS devices. These considerations are discussed in the Ap plieation Note AP-252, "Designing with the 80C5lBH. For more information on the individual devices and features listed in Table 1, refer to the Hardware De scriptions and Data Sheets of the specific device. 1-6 intel. MCS@-51 ARCHITECTURAL OVERVIEW Data Memory occupies a separate addrexs space from %OgrCt122 hkznory. Up to 64K bytes of exterttd RAM can be addreased in the externrd Data Memo~. The CPU generatea read and write signals RD and ~, as needed during external Data Memory accesses. External Program Memory and external Data Memory ~~ combined if-desired by applying the ~ ~d PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data memory. The lowest 4K (or SK or 16K) bytes of Program Memory can be either in the on-chip ROM or in an external ROM. This selection is made by strapping the ~ (External Access) pin to either VCC or Vss. In the 4K byte ROM devices, if the= pin is strapped to VcC, then program fetches to addresses 0000H through OFFFH are directed to the internal ROM. Program fetches to addresses 1000H through FFFFH are directed to external ROM. In the SK byte ROM devices, = = Vcc selects addresses (XtOOH through lFFFH to be internal, and addresses 2000H through F'FFFH to be external. In the 16K byte ROM devices, = = VCC selects addresses 0000H through 3FFFH to be internal, and addresses 4000H through FFFFH to be external. If the ~ pin is strapped to Vss, then all program fetches are directed to external ROM. The ROMleas parts must have this pin externally strapped to VSS to enable them to execute properly. The read strobe to externally: PSEN, is used for all external oro.cram fetches. PSEN LS activated for innot ProgramMemory Figure 3 shows a map of the lower part of the Program Memory. After reset, the CPU begins execution from location OWOH. AS shown in F@ure 3, each interrupt is assigned a tixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it commences execution of the serviee routine. External Interrupt O, for example, is assigned to location 0003H. If External Interrupt O is going to & used, its service routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as general purpose Program Memory. & ..-. (O033H) 002EH 002SH `s INTSRRUPT LOCATIONS 00IBH Ssvrm 0013H II 000SH 0003H a's `z~ l== 1 Po INSTR. m = ALE LArcn 270251-4 m% 1 EPROM AOOR R2S~ i 0000H Figure 4. Executing from External Program Memory 270251-3 Figure 3. MCW'-51 Program Memory The interrupt aeMce locations are spaced at 8-byte intervak 0U03H for External Interrupt O, 000BH for Tmer O, 0013H for External Interrupt 1, 00IBH for Timer 1, etc. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routinea can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. The hardware configuration for external program execution is shown in Figure 4. Note that 16 I/O lines (Ports O and 2) are dedicated to bus fictions during external Program Memory f~hes. Port O(PO in Figure 4) servex as a multiplexed address/data bus. It emits the low byte of the Program Counter (PCL) as an address, snd then goes into a float state awaiting the arrival of the code byte from the Program Memory. During the time that the low byte of the Program Counter is valid on PO, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 (P2 in Figure 4) emits the high byte of the Program Countex (WI-I). Then ~ strobex the EPROM and the code byte is read into the microcontroller. 1-7 MCS@-51 ARCHITECTURAL OVERVIEW Program Memory addresses are always 16 bits wide, even though the aotual amount of Program Memory used ntSy be kSS than 64K bytes. External prOq exeoutiorssacrifices two of the 8-bit ports, PO and P2, to the fisnction of addressing the Program Memory. Internal Data Memory is mapped in Figure 6. The memory space is shown divided into three bloeka, which are generally referred to as the Lower 128, the Upper 128, and SFR space. Internal Data Memory addresses are always one byte Wid%which implies an address space of only 256 bytes. However, the addressing modes for intemssl RAM ean in fact seeommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH awes one memory space, and indirect addresses higher than 7FH access a different memory space. Thus Figure 6 shows the Upthe per 128 and SFR spaceoccupying ssmeblockof addrq 80H throu~ FFH, slthoud they are physically separateentities; Data Memory Theright of Figure 2 shows the internal and exterhalf nal Dats Memory spaces available to the MCS-51 user. F@ure 5 shows a hardware configuration for accessing up to 2K bytes of external RAM. The CPU in this ease is executing from internal ROM. Port O serves as a multiplexed address/data bus to the RAM, and 3 lines of Port 2 are bein~d to page the RAM. The CPU generates = and WR signals as needed during exterial WM ameases. - BANK SELECT BRS IN `1 "{ `0{ 0'{ n 20H lSH 10H OBH eo{o Ill 7FH 2FH SN-ACORESSASLS SPACE (S~ A~ESSES O-7F) 1 1FH 17H OFH 07H 4 SANKSOF 8 REGIS7SRS RO-R7 RESETVALUEOF S7ACKPOIN7ER 1' I 270251-5 I 270251-7 Figure 7. The Lower 128 Bytes of internal RAM The Imwer 128 bytes of W are present in all MCS-51 devices as mapped in F@ure 7. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as RO through R7. Two bits in the Program Status Word (PSW) seleet which register bank is in use. This allows more effieient use of code space, since register instructions are shorter than instructions that use direet addreasiig. Figure 5. Accessing External Data Memory. If the Program Memory is Internal, the Other Bits of P2 are Available as 1/0. There ean be up to 64K bytea of external Data Memory. External Data Memory addresses can be either 1 or 2 bytes wide. One-byte addresses are often used in cxmjunction with one or more other 1/0 lines to page the R4M, as shown in Figure 5. Two-byte addresws ears atso be used, irz which case the high address byte is emitted at Port 2. FFH ~:.. UPP~ .-... ACCESSIBLE BV OIRECT AODRSSSING FFH , AC=IELE , SV INDIREC7 : AtORESSING ONLY SDH9 `m ACCESSIBLE LOWER SY 01REC7 128 ANO INC+REC7 o AGGRESSING EP `E~m SPWAL NC710N &oAmm~o CONTROLems TIMER RE-- STACKiolN7ER ACCUMULATOR ('nC.) W1 80H 270251-6 Figure 6. Internal Data Memory Figure 6. The Upper 128 Bytes of Internal RAM