MCS@51 MICROCONTROLLER FAMILY USER'S MANUAL ORDER NO.: 272383-002 FEBRUARY 1994 Intel Corporation makes no warrsnfy for the uee of ite products and assumes no responsibility for any ewors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notk Contact your local Intel sales office or your distributor to obtain the latest speoificationa before placing your product order. MDS is an ordering code only and is not usad ae a product name or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH trademark or products, are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH q Ofher brands and names are the properly of their respective owners, Additional copies of this document or other Intel literature maybe obtained from: Intel Corporation Literature Selas P.O. Box 7S41 Mt. Prospect, IL 6005S-7641 or call 1-800-879-4683 c-INTELCORPORATION, 1093 PAGE MCS" 51 CONTENTS MICROCONTROLLER c"*pTf== 1 FAMILY MCS 51 Family of Microcontrollers Archkedural Ovewiew .............................l-l USER'S MANUAL CHAPTER 2 MCS 51 Programmer's Guide and Instruction Set ..........................................2-l CHAPTER 3 8051, 8052 and 80C51 Hardware Description ...............................................3.l CHAPTER 4 8XC52J54/58 Hardware Description ............4-1 CHAPTER 5 8XC51 FX Hardware Description .................5-1 CHAPTER 6 87C51GB Hardware Description .................8-1 CHAPTER 7 83CI 52 Hardware Description ....................7-1 MCS@ 51 Family of Microcontrollers Architectural Overview 1 MCS@51 FAMILY OF MICROCONTROLLERS ARCHITECTURAL OVERVIEW CONTENTS INTRODUCTION PAGE .........................................1-3 CHMOS Devices .....".....'......." .....-.............I-5 M;~$&:RGA-~oN INMc- 51 Lo ical Separation of Program and Data h emoy ....................................................l+ Program Memo~ .........................................l-7 .................................................1-6 Data Memory ...............................................1 -8 THE MC951 INSTRUCTION SET .............1 -9 Program Status Word ..................................1 -9 Addressing Modes .....................................l-l O Arithmetic Instructions ...............................1-10 Logical lnstrudions Data Tran#ers ....................................l.l2 ...........................................l.l2 Boolean Instructions ..................................1-14 Jump Instructions ......................................1-16 CPU TIMING .............................................l-l7 Machine Cycles .........................................1-18 Interrupt Structure ......................................l.2O ADDITIONAL REFERENCES ...................1 -22 1-1 ir&L INTRODUCTION The8051 M~@.51 ARCHITECTURAL OVERVIEW is the original member of the MCW-51 family, and is the core for allMCS-51 devices. The features of the 8051 core are q 8-bit CPU optimized for control applications q Extensive Boolean processing (Single-blt logic) capabtilties q q q q q q q q q 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytesof on-chip Data RAM 32 bidirectional and individually addressable 1/0 lines Two 16-bit timer/counters Full duplex UART 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator The basic architectural structure of this 8051 core is shown in Figure L EXTERNAL INTERRUPTS ,, I I COUNTER INPUTS w II BUS CONTROL H 4 1/0 PORTS H 11 Po P2 PI P3 AODRESS/DATA Q SERIAL PORT TXO RXD 270251-1 Figure 1. Block Diagram of the 8051 Core 1-3 intd. MCS@-51 ARCHITECTURAL OVERVIEW 1-4 i~. MCS@'-5l ARCHITECTURAL OVERVIEW 1-5 i~. M~@.51 ARCHITECTURAL OVERVIEW * ----------- 8 1 1 1 1 1 1 1 I 1 PROORAMMrhtosv (REM ONLY) -------------FFFFw T - I o 8 0 0 8 0 I I I , 0 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 I , B I I $ s -----------------------t 8 I 1 I 8 I I I : o # 8 9 8 8 0 0 9 t # I , 1 : FfH: OATAMEMORY (RW/WRlT2) EXIERNALm EXTERNAL - 0 9 1 I : # G=o o 2STERNAL 0 1 0 @ * I : q - ---------- ..... 8 8 I I 0 I * 0 I I # I I I I I I 1 : 1 I I IN7ERNM ------ m.1 IN7ERNAL : : 0 9 * I I I 0000 --------.! 0: 9, e, 9 0 9 8 1 I ,1+ 00 1 q-------- 0000 --------..- J: -. -.-: tiR 1 I 1 1 0 1 1 I 1% Figure 2. MCW'-51 Memory Structure 270251-2 CHMOS Devices Functionally, the CHMOS devices (designated with "C" in the middle of the device name) me all fiuy compatible with the 8051, but being CMOS, draw less current than an HMOS counterpart. To further exploit the power savings available in CMOS circuitry, two reduced power modes are added q MEMORY ORGANIZATION MCS@-51 DEVICES Logical Separation Data Memory IN of Program and Software-invoked Idle Mode, during which the CPU is turned off while the RAM and other on-chip peripherals continue operating. In this mode, current draw is reduced to about 15% of the current drawn when the device is fully active. Software-invoked Power Down Mode, during which all on-chip activities are suspended. The on-chip RAM continues to hold its data. In this mode the device typically draws less than 10 pA. q AU MCS-51 devices have separate address spacea for Program and Data Memory, as shown in Figure 2. The logical separation of Program and Data Memory allows the Data Memory to be acceased by 8-bit addressea, which can be more quickly stored and manipulated by an 8-bit CPU. Nevertheless, ld-bh Data Memory addresses can also be generated through the DPTR register. Program Memory can only be read, not written to. There can be up to 64K bytes of Program Memory. In the ROM and EPROM versions of these devices the loweat 4K, 8K or 16K bytes of Program Memory are provided on-chip. Refer to Table 1 for the amount of on-chip ROM (or EPROM) on each device. In the ROMleas versions all Program Memory is external. The read strobe for external Program Memory is the signal PSEN @rogram Store Enable). Although the 80C51BH is functionally compatible with its HMOS counterpart, s~lc differeneea between the two types of devices must be considered in the design of an application circuit if one wiahea to ensure complete interchangeability between the HMOS and CHMOS devices. These considerations are discussed in the Ap plieation Note AP-252, "Designing with the 80C5lBH. For more information on the individual devices and features listed in Table 1, refer to the Hardware De scriptions and Data Sheets of the specific device. 1-6 intel. MCS@-51 ARCHITECTURAL OVERVIEW Data Memory occupies a separate addrexs space from %OgrCt122 hkznory. Up to 64K bytes of exterttd RAM can be addreased in the externrd Data Memo~. The CPU generatea read and write signals RD and ~, as needed during external Data Memory accesses. External Program Memory and external Data Memory ~~ combined if-desired by applying the ~ ~d PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data memory. The lowest 4K (or SK or 16K) bytes of Program Memory can be either in the on-chip ROM or in an external ROM. This selection is made by strapping the ~ (External Access) pin to either VCC or Vss. In the 4K byte ROM devices, if the= pin is strapped to VcC, then program fetches to addresses 0000H through OFFFH are directed to the internal ROM. Program fetches to addresses 1000H through FFFFH are directed to external ROM. In the SK byte ROM devices, = = Vcc selects addresses (XtOOH through lFFFH to be internal, and addresses 2000H through F'FFFH to be external. In the 16K byte ROM devices, = = VCC selects addresses 0000H through 3FFFH to be internal, and addresses 4000H through FFFFH to be external. If the ~ pin is strapped to Vss, then all program fetches are directed to external ROM. The ROMleas parts must have this pin externally strapped to VSS to enable them to execute properly. The read strobe to externally: PSEN, is used for all external oro.cram fetches. PSEN LS activated for innot ProgramMemory Figure 3 shows a map of the lower part of the Program Memory. After reset, the CPU begins execution from location OWOH. AS shown in F@ure 3, each interrupt is assigned a tixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it commences execution of the serviee routine. External Interrupt O, for example, is assigned to location 0003H. If External Interrupt O is going to & used, its service routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as general purpose Program Memory. & ..-. (O033H) 002EH 002SH `s INTSRRUPT LOCATIONS 00IBH Ssvrm 0013H II 000SH 0003H a's `z~ l== 1 Po INSTR. m = ALE LArcn 270251-4 m% 1 EPROM AOOR R2S~ i 0000H Figure 4. Executing from External Program Memory 270251-3 Figure 3. MCW'-51 Program Memory The interrupt aeMce locations are spaced at 8-byte intervak 0U03H for External Interrupt O, 000BH for Tmer O, 0013H for External Interrupt 1, 00IBH for Timer 1, etc. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routinea can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. The hardware configuration for external program execution is shown in Figure 4. Note that 16 I/O lines (Ports O and 2) are dedicated to bus fictions during external Program Memory f~hes. Port O(PO in Figure 4) servex as a multiplexed address/data bus. It emits the low byte of the Program Counter (PCL) as an address, snd then goes into a float state awaiting the arrival of the code byte from the Program Memory. During the time that the low byte of the Program Counter is valid on PO, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 (P2 in Figure 4) emits the high byte of the Program Countex (WI-I). Then ~ strobex the EPROM and the code byte is read into the microcontroller. 1-7 MCS@-51 ARCHITECTURAL OVERVIEW Program Memory addresses are always 16 bits wide, even though the aotual amount of Program Memory used ntSy be kSS than 64K bytes. External prOq exeoutiorssacrifices two of the 8-bit ports, PO and P2, to the fisnction of addressing the Program Memory. Internal Data Memory is mapped in Figure 6. The memory space is shown divided into three bloeka, which are generally referred to as the Lower 128, the Upper 128, and SFR space. Internal Data Memory addresses are always one byte Wid%which implies an address space of only 256 bytes. However, the addressing modes for intemssl RAM ean in fact seeommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH awes one memory space, and indirect addresses higher than 7FH access a different memory space. Thus Figure 6 shows the Upthe per 128 and SFR spaceoccupying ssmeblockof addrq 80H throu~ FFH, slthoud they are physically separateentities; Data Memory Theright of Figure 2 shows the internal and exterhalf nal Dats Memory spaces available to the MCS-51 user. F@ure 5 shows a hardware configuration for accessing up to 2K bytes of external RAM. The CPU in this ease is executing from internal ROM. Port O serves as a multiplexed address/data bus to the RAM, and 3 lines of Port 2 are bein~d to page the RAM. The CPU generates = and WR signals as needed during exterial WM ameases. - BANK SELECT BRS IN `1 "{ `0{ 0'{ n 20H lSH 10H OBH eo{o Ill 7FH 2FH SN-ACORESSASLS SPACE (S~ A~ESSES O-7F) 1 1FH 17H OFH 07H 4 SANKSOF 8 REGIS7SRS RO-R7 RESETVALUEOF S7ACKPOIN7ER 1' I 270251-5 I 270251-7 Figure 7. The Lower 128 Bytes of internal RAM The Imwer 128 bytes of W are present in all MCS-51 devices as mapped in F@ure 7. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as RO through R7. Two bits in the Program Status Word (PSW) seleet which register bank is in use. This allows more effieient use of code space, since register instructions are shorter than instructions that use direet addreasiig. Figure 5. Accessing External Data Memory. If the Program Memory is Internal, the Other Bits of P2 are Available as 1/0. There ean be up to 64K bytea of external Data Memory. External Data Memory addresses can be either 1 or 2 bytes wide. One-byte addresses are often used in cxmjunction with one or more other 1/0 lines to page the R4M, as shown in Figure 5. Two-byte addresws ears atso be used, irz which case the high address byte is emitted at Port 2. FFH ~:.. UPP~ .-... ACCESSIBLE BV OIRECT AODRSSSING FFH , AC=IELE , SV INDIREC7 : AtORESSING ONLY SDH9 `m ACCESSIBLE LOWER SY 01REC7 128 ANO INC+REC7 o AGGRESSING EP `E~m SPWAL NC710N &oAmm~o CONTROLems TIMER RE-- STACKiolN7ER ACCUMULATOR ('nC.) W1 80H 270251-6 Figure 6. Internal Data Memory Figure 6. The Upper 128 Bytes of Internal RAM I 80H NO SIT-AOORSSSABLE SPACES AVAIUBLE AS S7ACK SPACEIN DEVICESWMI 256 BWES RAM NOT IMPLE14EN7ED 8051 IN 270251-8 I-6 in~. M~@-51 ARCHITECTURAL OVERVIEW CTIAC] b 1 CARRYFLAGRECEIVESCMi/fmw; FROU BIT 1 Of ALU OPERANOS FOIRSIIRBO[ A a a OVI * A I P I KWO PARllY OFACCLWUIATORSS7 ~ NARoWARC 1 IF IT CONTAINS TO AN 000 NUMBEROF 1S, OTHERWISE 171SRESE7TO0 -- Psw 1 USER OEFINABLE FUG Psw6-- AUXILIARYCARRYFLAG RECEIVES CARRYOUT FROM B171 OF AOOMON OPERANOS nw5 GENERALPURPOSES7ATUS FLAG Psw 2 OVERFLOWFIAO SET BY ARITIMCW OPERAl!ONS REGtS7ER SW'% BANK -. .- t .. . ... .. . . . Psw3 REOSJER BANK SELECT O Bll 270251-10 --------- Figure 1u. Psw (Progrsm ssssus worn) Register m mc5w-51 . . . . . .- t2evtces The next 16 bytea above the register bankBform a block of bit-addressable memory apace. The MCS-51 instruction set includes a wide seleetion of single-blt instructions, and the 128 bits in this area can be directly addressed by these irsstmctions. The bit addreascs in this area are W)H through 7FH. All of the bytes in the LQwer 128 can be accessed by either direct or indirect addressing. The Upper 128 (Figure 8) can only be accessed by indirect addressing. The Upper 128 bytes of RAM are not implemented in the 8051, but me in the devices with 256 bytea of RAM. (Se Table 1). Figure 9 gives a brief look at the Special Funotion Register (SFR) space. SFRS include the Port latchea, timers, pe2iphA controls, etc. l%ese registers can only& -seal by dmect addressing. In general, all MCS-51 microcontrollers have the same SFRB as the 8051, and at the same addresses in SFR space. However, enhancements to the 8051 have additional SFRB that are not present in the 8051, nor perhaps in other proliferations of the family. !%teers addresses in SFR mace are both byte. and bit. addressable. The blt-addre&able SFRS are `those whose address ends in 000B. The bit addresses in this ares are 80H throUgh FFH. THE MCS@-51 INSTRUCTION SET All members of the MCS-51 family execute the same instruction set. The MCS-51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal MM to facilitate byte operations on small data structures. The instruction sd provides extensive support for one-bit variables as a separate data t% allowing direct blt manipulation in control and logic systems that require Boolean prmessirsg. An overview of the MCS-51 instruction set is prrsented below, with a brief description of how certain instructions might be used. References to "the assembler" in this discussion are to Intel'sMCS-51 Macro Assembler, ASM51. More detailed information on the instruction set can be found in the MCS-51 Macro Assembler User's Guide (Grder No. 9W3937 for 1S1SSystems, Grder No. 122752 for DOS Systems). EOH "u m PORT .3 Porn 2 POR7 1 B RE~MAPPSO POR7S AOORESSES 7NAT END IN OH OR EN ARCALSO B~-AOORESSABLE Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The PSW, shown in Figure 10, resides in SFR space. It contains the Csrry bi~ the Auxdiary Carry (for BCD operations), the two register bank select bits, the Gvesflow flag, a Parity bit, and two userdefinable status tlags. The Carry bit, other than serving the functions of a Carry bit in arithmetic operations, also sesws as the "Accumulator" for a number of Boolean operations. 80H AOH 90H -POR7 PINS -ACCUMULATOR -Psw (E7c.) J-A--I 270251-9 Figure 9. SFR Spsce 1-9 MCS@-51 ARCHITECTURAL OVERVIEW The bits RSOand RSl are wed to select one of the four register banks shown in Figure 7. A number of instructions refer to these RAM locations as RO through R7. The selection of which of the four banks is being referred to is made on the basis of the bits RSO and RS1 at execution time. The Parity bit reflects the number of 1s in the Accumulator P = 1 if the Accumulator contains an odd number of 1s, and P = O if the Accumulator contains an even number of 1s. Thus thenumber of 1s in the Accumulator plus P is always even. Two bits in the PSW are uncommitted and maybe used as general purpose status flags. IMMEDIATE CONSTANTS The value of a constant can follow the opcode in Program Memory. For example, MOV A, # 100 loads the Accumulator with the decimal number 100. The same number could be specified in hex digitz as 64H. INDEXED ADDRESSING Addressing are as follows Modes The addressing modes in the MCS-51 instruction set only Program Memory can be amessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program Memory. A Id-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is setup with the table entry number. The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer. DIRECT ADDRESSING In direct addressing the operand is specitied by an 8-bit addreas field in the instruction. Only internal Data RAM and SFRS can be directly addressed. INDIRECT ADDRESSING Another type of indexed addreaaing is used in the "case jump" instruction. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator &ta. Arithmetic Instructions In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be RO or RI of the selected register bank, or the Stack Pointer. The addreas register for id-bit addresses can only be the id-bit "data pointer" register, DPTR. REGISTER INSTRUCTIONS Themenu of arithmetic instructions is listed in Table 2. The table indicates the addressing modes that can be used with each instruction to access the operand. For example, the ADD A, instruction can be written as ADD ADD ADD ADD A,7FH A,@RO A,R7 A, # 127 (direct addressing) (indirect addressing) (register addressing) (iediate constant) The register banks, containing registers RO through R7, can be accemed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode elirninatez an addreas byte. When the instruction is executedj one of the eight registers in the selected bank is amessed. One of four banks is selected at execution time by the two bank select bits in the PSW. REGISTER-SPECIFIC INSTRUCTIONS The execution times listed in Table 2 assume a 12 MHz clock frequency. All of the arithmetic instructions execute in 1 ps except the INC DPTR instruction, which takes 2 W, snd the Multiply and Divide instructions, which take 4 ps. Note that any byte in the internal Data Memory space can be incremented or decremented without going through the Accumulator. One of the INC instructions operates on the Id-bit Data Pointer. The Data Pointer is used to generate 16-bit addresses for external memory, w being able to increment it in one 16-bit operation is a usefirl feature. The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the Id-bit product into the concatenated B and Accumulator registers. Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is Inneeded to point to it. The opcode itself does that. structions that refer to the Accurrdator as A assemble as accumulator-specific opcmdes. 1-1o inl# MCS@-51 ARCHITECTURAL OVERVIEW Table 2 A Ust of the MCS@I-51 Arithmetic Mnemonic Operation Dk I A= A+ Instructions Modes Rq lmm Execution Time (@ Addressing Ind ADD I SUBB A, I A, x I X I x X I x X I x X ] 1 1 I ADDOA, A= A= A+< byte>+C A­-C x I I X I x X I x X I x I 1 1 INC I I I lhJC DEC DEC MUL A DPTR A I I I I A=A+l =+l Accumulator onlv INC . 11-1 121 Ill 1 DPTR = DpTR + 1 A= A-l = ­1 I Data Pointer only I x I A Accumulator only x ACC and B ACC and B x only only I AB AB B.A=Bx 4 I DIV I I A = Int [A/B] B = MOd [A/Bl Decimal Adjust I Ill 4 I IDAA I Accumulatoronly The DIV AB instruction divides the Accumulator by the data in the B register and leevea the 8-bit quotient in the Accumulator, and the 8-bit remainder in the B register. Oddly enough, DIV AB finds lees use in arithmetic "divide" routines than in radix eonversions and pro~ble shift operstioILs. k example of the use of DIV AB in a radix conversion will be given later. In s~ operations, dividing a number by 2n shifts its n bits to the right. Using DIV AS to perform the division eompletcs the shift in 4 p.s and leaves the B register holding the bits that were shifted out. The DA A instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC instructions should always be followed by a DA A operation, is also in BCD. Note that DA to ensure that the red A will not convert a binary number to BCD. The DA A operation produces a meaningfid result only as the second step in the addition of two BCD bytes. Table 3. A Uet of the MCS@J-51Logical Instructions I ANL ANL ANL ORL ORL ORL XRL XRL XRL Mnemonic A,< byte> ,A , #data I A=A = = Operation Dir Addressing Ind Modes I Imm Execution Time (ps) I Reg .AND. .AND. A x x x x x x 1 1 2 I .AND. #data A,< byte> ,A , #data A,< byte> ,A , #data IA= A.OR. = .OR. A I = .OR. #data A = A .XOR. I = = .XOR. A .XOR. #data I X1X1X1X x x X1X1X xI I X I 1 1 2 x I 1 1 2 CRL A A=OOH Accumulator only Accumulator 1 CPL IRL A A A= .NOT. A only I Ill I 1 1 1 1 I Rotate ACC Left 1 bit I Accumulator onlv Accumulator only Accumulator only Accumulator Accumulator only RLC RR RRC SWAP A A A A I Rotate Left through Csrry Rotate ACC Right 1 bit Rotate Right through Carry Swap Nibbles in A 1-11 I onlv 1 irrtel. Logical Instructions MCS@-51 ARCHITECTURAL OVERVIEW Table 3 shows the list ofMCS-51 logical instructions. The instructions that perform Boolean operations (AND, OIL Exclusive OIL NOT) on bytes perform the operation on a bit-by-bit bssis. That is, if the AecumuIator contains 001101OIB and contains O1OIOOIIB,then ANL A, The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This is a useful operation in BCD manipulations. For exampie+ if the Accumulator contains a binary number which is known to be leas thsn IQ it can be qnickly converted to BCD by the following code: MOV DIV SWAP ADD B,# 10 AB A A,B will leave the Accumulator holding OOO1OOOIB. The addrcasing modes that can be used to access the operand are listedin Table 3. Thus, the ANL A, instruction may take any of the forms ANL ANL ANL ANL A,7FH A,@Rl A,R6 A, # 53H (direct addressing) (indirect addressing) (register addressing) (immediate constant) Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and the ones digit in the B register. The SWAP and ADD instructions move the tens digit to the high nibble of the Accumulator, and the onea digit to the low nibble. Data Transfers INTERNAL RAM AU of the logical instructions that are Accumulatorspecflc execute in lps (using a 12 MHz clock). The othem take 2 ps. Note that Boolean operations can be performed on any byte in the lower 128 internal Data Memory space or the SFR space using direct addressing, without having to use the Accumulator. The XRL , #data instruction, for example offets a quick and easy way to invert port bits, as in XRL Pl,#oFFH Table 4 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used with each one. Wkh a 12 MHz clock, all of these instructions execute in either 1 or 2 ps. The MOV < dest >, < src > instruction allows dats to be transferred between any two internal RAM or SFR lwations without going through the Accumulator. Remember the Upper 128 byes of data RAM can be acwased only by indirect addressing, and SFR space only by direct addressing. Note that in all MCS-51 devices, the stack resides in on-chip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP), then copies the byte into the stack. PUSH and POP use only dkcct addressing to identify the byte being saved or restored, If the operation is in response to an interrupt, not using the Accumulator saves the time and effort to stack it in the service routine. The Rotate instructions (3U & RLC A, etc.) shift the Aeeurtmlator 1 bit to the MI or right. For a left rotation, the MSB rolls into the LSB position. For a right rotation, the LSB rolls into the MSB position. Table 4. A List of the MCS@-51 Data Tranafer Mnemonic MOV A, A = Instructions that Access Internal Data Memory Space Addressing Dir Ind Modes Imm Execution Time (ps) Operation Reg x x x x x x x x x 1 1 2 2 MOV MOV MOV PUSH POP XCH ,A , = A = DPTR = 16-bit immediate constant. INC SP: MOV "@'SP', MOV , "@SP": DEC SP ACC and exchange data ACC and @Riexchange low nibbles 1-12 x x x x x x DPTR,#data16 2 2 x x x 1 1 A, XCHD A,@Ri i~o MCS@-51 ARCHITECTURAL OVERVIEW but the stack itself is accessed by indirect addressing using the SP register. This means the stack can go into the Upper 128, if they are implemented, but not into SFR space. In devices that do not implement the Upper 128, if the SP points to the Upper 128, PUSHed bytes are lost, and POPped bytes are indeterminate. The Data Transfer instructions include a id-bit MOV that can be used to initialise the Data Pointer (DPTR) for look-up tables in Program Memory, or for Id-bit external Data Memory accesw. The XCH A, instruction causes the Amulator snd addressed byte to exchsnge data. The XCHD A, @Ri instruction is similar, but only the low nibbles are involved in the exchange. To see how XCH and XCHD can be used to fatitate data manipulations, consider first the problem of shit%ing an 8digit BCD number two digits to the right. Figure 11 shows how this can be done using direct MOVS, and for comparison how it can be done using XCH instructions. To aid in understanding how the code works, the contents of the registers that are holding the BCD number and the content of the Accumulator are shown alongside each instruction to indicate their status after the instruction has been executed. Atler the routine has been executed, the Accumulator contains the two digits that were shitled out on the right. Doing the routine with direct MOVS uses 14 code bytes and 9 ps of execution time (assuming a 12 MHs clock). The same operation with XCHS uses less code and executes almost twice as fast. To right-shift by an odd number of digits, a one-digit shift must be executed. Figure 12 shows a sample of code that will right-shii a BCD number one digi~ using the XCHD instruction. Again, the contents of the registers holding the number and of the Accumulator are shownalongside achinstruction. e MOV MOV Rl, #2EH RO,#2DH m loop for R1 = 2EH .00P MOV XCHD SWAP MOV DEC DEC CJNE A,@Rl A,@RO A @Rl,A RI RO Rl,#2AH,LOOP 00 12 34 56 78 00 12 34 56 78 00 12 34 58 78 00 12 34 58 67 00 12 34 58 67 00 12 34 56 67 00 12 36 45 67 00 18 23 45 67 0s 01 22 45 67 06 01 23 45 67 00 01 23 45 67 76 76 67 67 67 67 45 23 01 00 06 Imp for RI = 2DH loop for R1 = 2CH: ioop for RI = 2BH: CLR XCH A A,2AH n3JMm MOV A,2EH MOV 2EH2DH MOV 2CH:2BH